Some semiconductor devices utilize semiconductor-on-insulator (SOI) technology, in which a thin layer of a semiconductor, such as silicon, is separated from a semiconductor substrate by a relatively thick electrically insulating layer. This thick electrically insulating layer is also referred to as a buried oxide (BOX) layer. The semiconductor layer typically has a thickness of a few nanometers, whereas the semiconductor substrate typically has a thickness of a few tens of nanometers.
SOI technology offer certain advantages compared to traditional bulk technology for Complementary Metal Oxide Semiconductor (CMOS) devices. CMOS devices include nMOSFET transistors and pMOSFET transistors both formed in the thin silicon layer which overlies the buried oxide (BOX) layer. SOI technology allows CMOS devices to operate at a lower power consumption while providing the same performance level.
One particular type of SOI technology that is helping to allow for continued CMOS scaling is fully depleted SOI (FDSOI). As opposed to a partially depleted SOI (PDSOI) device, in an FDSOI device a relatively thin semiconductor channel layer is provided over the buried oxide (BOX) layer, such that the depletion region of the device covers the whole layer. FDSOI devices may provide advantages such as higher switching speeds and a reduction in threshold voltage roll off, as compared to PDSOI devices, for example.
To improve CMOS device performance, stress may be introduced into the channels of the field effect transistors (FETs). When applied in a longitudinal direction (i.e., in the direction of current flow), tensile stress is known to enhance electron mobility (i.e., n-channel FET drive currents) while compressive stress is known to enhance hole mobility (i.e., p-channel FET drive currents).
Typical methods for enhancing channel stress in a semiconductor device involve the use of a blanket implantation across an entire semiconductor substrate. A more localized implantation approach is disclosed in U.S. published patent application no. 2013/0217198. A localized implant into a gate region prior to gate etch is performed for enhancing the channel stress of the semiconductor device.
Another approach for enhancing channel stress in a semiconductor device involves embedding source/drain stressor material in stress cavities in the source/drain regions of a MOSFET. Silicon germanium (SiGe) may be used in pMOSFETs to induce compressive strain in the channel region, and silicon carbide (SiC) may be used in nMOSFETs to induce tensile strain in the channel region. The source/drain stressor material may be heavily doped in-situ to avoid implant damage to the stressor that can degrade the channel stress.
Despite the existence of such configurations, further enhancements in SOI devices may be desirable in some applications.